1. Field of the Invention
The present invention relates to a full wave rectifying circuit used in a semiconductor integrated circuit or the like, and more particularly, it relates to a full wave rectifying circuit of improved accuracy where single input is rectified on the full wave basis.
2. Description of the Prior Art
A prior art full wave rectifying circuit will be described with reference to FIG. 9. FIG. 9 is a circuit diagram showing the prior art full wave rectifying circuit. The full wave rectifying circuit in FIG. 9 includes an a.c. signal source 50, a d.c. voltage source 51 outputting voltage V.sub.ref4, a coupling capacitor 52, differential twin transistors Q63, Q64, resistances 53, 54, 56, 57, 58, 59, and a constant current source 55 supplying constant current I.sub.7. The resistances 53, 54, 57, 58, 59, the constant current source 55 and the transistors Q63, Q64 together constitute a single-input differential output converting circuit. Single input is converted by the single-input differential output converting circuit into a differential output and then output from an output terminal connected to collectors of the transistors Q63, Q64. The full wave rectifying circuit further includes coupling capacitors 60, 61, differential twin transistors Q60, Q61, resistances 62, 63 connected to the d.c. voltage source 51 for supplying d.c. voltage V.sub.ref4 to bases of the transistors Q60, Q61, a resistance 65 grounding emitters of the differential twin transistors Q60, Q61, a resistance 64 connecting collectors of the differential twin transistors Q60, Q61 to a voltage terminal 67, an output transistor Q62 having its base connected to the collectors of the differential twin transistors Q60, Q61, and a constant current source 66 connected to an emitter of the output transistor Q62 for supplying constant current I.sub.8.
Then, an operation of the full wave rectifying circuit shown in FIG. 9 will be described. FIGS. 10(a) to 10(g) are diagrams illustrating signal waveforms at various junctions of the full wave rectifying circuit shown in FIG. 9. An a.c. signal is transmitted from the a.c. signal source 50 to a junction Z marked in FIG. 9, or a base of the transistor Q63, via the coupling capacitor 52. The voltage V.sub.ref4 is applied to bases of the transistors Q63, Q64 by the d.c. voltage source 51. The a.c. signal input to the junction Z is converted into a differential output by the differential twin transistors Q63, Q64 and then input via the coupling capacitors 60, 61 to junctions X and Y, respectively. The voltage V.sub.ref4 is applied via the resistances 62, 63 to the junctions X and Y by the d.c. voltage source 51. Voltage waveforms at the junctions X and Y are waveforms of voltage V.sub.x and voltage V.sub.y shown in FIGS. 10(b) and 10(c). As shown in these figures, the waveforms of the voltages V.sub.x, V.sub.y are waveforms opposite in phase to each other.
When the voltage V.sub.x at the junction X and the voltage V.sub.y at the junction Y satisfy the relation of V.sub.x &gt;V.sub.y, that is, in the event of a first semicycle, the transistor Q60 turns on while the transistor Q61 turns off. Assuming now that resistance values of the resistances 64, 65 are R.sub.64, R.sub.65, values of currents flowing in the resistances 64, 65, respectively, are I.sub.R64, I.sub.R65, and base-emitter voltage of the transistor Q.sub.60 is V.sub.BE1, the currents I.sub.R64, I.sub.R65 are expressed by the following formula: ##EQU1##
Assuming that supply voltage of the circuit shown in FIG. 9 is V.sub.CC, output voltage is V.sub.OUT4, and voltage at a junction U is V.sub.U, V.sub.U and V.sub.OUT4 are given by the following formulas: ##EQU2##
When the voltage V.sub.x at the junction X and the voltage V.sub.y at the junction Y satisfy the relation of V.sub.x &lt;V.sub.y, or in the event of the first semicycle, the transistor Q60 turns off while the transistor Q61 turns on. In this situation, assuming that the base-emitter voltage of the transistor Q61 is V.sub.BE2, the currents I.sub.R64, I.sub.R65 flowing in the resistances 64, 65 are given by the following formula: ##EQU3##
Furthermore, the voltage V.sub.U at the junction U and the output voltage V.sub.OUT4 are given by the following formulas: ##EQU4##
Thus, the output voltage V.sub.OUT4 exhibits a waveform rectified on the full wave basis as illustrated in FIG. 10(g). The currents I.sub.R64, I.sub.R65 and the voltage V.sub.U exhibit waveforms with a criterion of the current or voltage expressed in the following formula, as illustrated in FIGS. 10(c), 10(d) and 10(e): ##EQU5##
In the course of a transition from a condition V.sub.x &gt;V.sub.y to another condition V.sub.x &lt;V.sub.y as to the voltages V.sub.x and V.sub.y, that is, in the course of a transition from a condition that the transistor Q60 is in its ON-state while the transistor Q61 is in its OFF-state to another condition that the transistor Q60 is in its OFF-state while the transistor Q61 is in its ON-state, there exists a state where both the transistors Q60 and Q61 are in ON-state. Under the condition that both the transistors Q60 and Q61 are in ON-state, the currents I.sub.R64, I.sub.R65 branch into both the transistors Q60, Q61. It is apparent that the base-emitter voltage V.sub.BE1 or V.sub.BE2 under this condition is different in level from the voltage V.sub.BE1 or V.sub.BE2 under a condition that all of the currents I.sub.R64 and I.sub.R65 flow in either the transistor Q60 or the transistor Q61. Variations in the voltage V.sub.BE1 or V.sub.BE2 is a factor of an error caused in the output voltage V.sub.OUT4 as will be recognized in the formulas (3) and (6), and as the input a.c. signal is decreased, a rate of the error is increased. FIG. 11 is an enlarged diagram of a portion Ar encircled by broken line in the output voltage V.sub.OUT4 illustrated in FIG. 10(g). As shown in FIG. 11, the waveform may be made blunt in a region where the output voltage V.sub.OUT4 related to small input voltage V.sub.IN becomes small. In FIG. 11, although an ideal waveform of the output is drawn by broken line, the output practically exhibits a waveform as drawn by solid line. FIG. 12 shows an input/output characteristic of the full wave rectifying circuit shown in FIG. 9. In the full wave rectifying circuit shown in FIG. 9, linearity of the input/output characteristic is detracted for the above-mentioned reasons.
The prior art full wave rectifying circuit is configured as discussed above, and therefore, there are disadvantages that it requires a single-input differential output converting circuit for converting a single input into a differential output so as to rectify the single input on the full wave basis and besides that the linearity of the output voltage V.sub.OUT4 rectified on the full wave basis is detracted in a region where input voltage is small because of variations in the base-emitter voltages V.sub.BE1 and V.sub.BE2.